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Chapter 7:
Data Compression Engines aboard a Satellite
This chapter describes the hardware implementation of SAMVQ and HSOCVQ algorithms for near-lossless data compression onboard satellites. Three top-level topologies were considered to meet the initial design objective, including a digital signal processor (DSP) engine-based approach, a high-performance, general-purpose CPU-based approach, and an application-specific integrated circuit (ASIC) or field programmable gate array (FPGA) approach. The resulting onboard data compression engines were evaluated for various configurations. After studying the topologies, the hardware and software architectural options, and candidate components, an architectural preference was placed on a hardware compressor with modularity and scalability. The performance trade-off studies for these architectures showed that the best performance and scalability could be achieved using dedicated compression engines (CEs) based on an ASIC/FPGA topology. The advantages of the ASIC/FPGA approach include the ability to • Apply parallel processing to increase throughput, • Provide for successive upgrades of compression algorithms and electronic components over a long term, • Support high-speed direct memory access (DMA) transfers for data read and write operations, • Optimize the scale of the design to mission requirements, and • Provide data integrity features throughout the data handling process.
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