Integrated circuits are built through a sequence of patterning steps. If the transistor shown in Fig. 6.1 is going to be contacted electrically so that it functions properly, the contact to the gate must physically connect to the gate and not short electrically to the source or drain. This requires that the pattern created at the contact-masking step be placed correctly on top of the pre-existing transistor structures. As one can see from Fig. 6.1, this placement does not need to be perfect, but it must be within certain tolerances. Transistors will function so long as the contacts have sufficient overlap with the appropriate parts of the transistor and do not contact the parts of the transistor from which they are supposed to be electrically isolated.
The lateral positioning between layers comprising integrated circuits is called overlay (see Fig. 6.2), which is defined precisely in SEMI Standard P18-92 as follows:
Overlay - A vector quantity defined at every point on the wafer. It is the difference O between the vector position P1 of a substrate geometry, and the vector position of the corresponding point P1 in an overlaying pattern, which may consist of photoresist:
As feature sizes shrink, so do the overlay tolerances between layers (see Table 6.1). While overlay is a vector quantity, the quantities in Table 6.1 are, by convention, the maximum tolerable magnitudes for overlay in either the X or Y direction. A related quantity, registration, is defined similarly to overlay:
Registration - A vector quantity defined at every point on the wafer. It is the difference R between the vector position P1 of a substrate geometry, and the vector position of the corresponding point P0 in a reference grid:
Note that overlay is a relative quantity, while registration is an error compared to an absolute standard P0.