Translator Disclaimer
In previous chapters we gave a broad general discussion of the steps for producing copper damascene interconnect structures with the aim of putting related issues in perspective. Now we will revisit some of these issues and highlight details of the practice preferred at present in implementing this type of process in production. Figure 49 outlines the essential steps of the process sequence. The individual steps we will focus on specifically are the precleaning of the metal inside vias before barrier deposition, deposition of an adhesion/diffusion barrier for Cu, and Cu deposition itself. The latter will include deposition of a Cu seed layer for ECP either by IMP or by CVD, and damascene filling by ECP or CVD. We will not examine any further the patterning of the dielectric and the planarization of the metal, although in both areas process optimization is on-going. This applies in particular to the formation of dual-damascene structures in the ILD, as aspect ratios become larger in SiO2, and as ILDs with lower k are being introduced. Also note that the examples we will give involve mostly Cu with undoped SiO2 as an ILD. This is the present stage of production, whereas the use of low-k ILDs is in the development phase. We will close this chapter with an outlook on future directions.
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