Access to eBooks is limited to institutions that have purchased or currently subscribe to the SPIE eBooks program. eBooks are not available via an individual subscription. SPIE books (print and digital) may be purchased individually on SPIE.Org.

Contact your librarian to recommend SPIE eBooks for your organization.
Chapter 4:
ADC Architectures for Image Sensors
Abstract
Almost every ADC architecture has been implemented on an image sensor in some form. This chapter is a survey of ADC architectures and an introduction to the characteristics and issues they bring into an image sensor signal chain. Each stand-alone architecture is identified as best for serial, column-parallel, pixel-parallel implementation, or combination thereof. This identification is given in the section title of each architecture to make it easier to identify the types of converters for a particular application. The flash ADC is one of the simplest and highest-speed ADCs. In fact, we can assume that its name is derived from its speed and that the digital result is available in real time in a “flash.” Flash ADCs were used extensively in digital video processing before being supplanted by more efficient architectures. Flash ADCs use a resistor ladder to generate a sequence of voltages between high and low ADC references. Each of these voltages is compared to the input through its own comparator. Comparators with resistor references below the input will flip, generating a thermometric code output across the entire comparator bank, as shown in Fig. 4.1(b). The thermometric code will then be converted to binary, typically using a cascade adder-based decoder. This can all be done with static elements; however, designers often use clocked comparators so that a decision can be made after the input settles.
Online access to SPIE eBooks is limited to subscribing institutions.
CHAPTER 4
40 PAGES


SHARE
Back to Top