The general concept of pipelining is powerful. Generically, pipelining is splitting any temporally sequential task into individual smaller operations for execution at the same time. An old example of this that is quite pertinent to image sensors takes us to the original 2D image sensor multiplexor (mux) circuits. These muxes were created out of a 2D array of switches, whereby each detecting element had one switch for the x direction and one switch for the y direction. Detector current could be accessed by a centralized transimpedance circuit when both switches were closed. All detector elements could be scanned sequentially to transmit and recompose a 2D image. This process required a lot of time to settle each detector, especially for very low detection currents. Engineers figured out that if the pixel could perform more of the work and integrate while other pixels were being read out, image sensor performance could be vastly improved. This lead to integration capacitance in each pixel and a pipelining of the operations. While one pixel was being read out of the mux, all of the other pixels could continue to integrate photocurrent. Further combinations of parallelism and pipelining have led to the high-performance image sensors in use today. A fun thought experiment would be to imagine how long it would take to read out a modern 10-MPixel sensor even with high photocurrents of 100 fA per pixel (which is unrealistically high for tiny-pixel visible sensors) with an original analog mux. Assuming that it could even be done, it would probably take on the order of 1 minute to settle every detector node, which would lead to a read-out time of 19 or 20 years. By that time, the subject of your photo might have become bored and wandered off. It is probably not too strong a statement to say virtually every modern image sensor contains some form of pipelining. Pipelining is still one of the most powerful techniques to improve performance in all manner of circuits, and ADCs are no exception.
As we discovered in the previous chapter, pipeline ADCs are used in more than two-thirds of industrial ADC products because they are the fastest architecture for medium to high resolutions and they are one of the most efficient architectures for power per LSB for medium to high resolutions. Their power and layout area can be reduced greatly after the MSB stage, even further increasing their efficiency. We will see in this chapter that most pipeline ADCs have almost no contributed noise from the analog-to-digital sub-converter (ADSC) operation because the error is mathematically canceled all the way down to the final ADSC, where the impact of noise is small. Additionally, pipeline ADCs are able to move many of the analog constraints into the digital realm through digital calibration routines. This reduces power and area constraints for design of analog components such as amplifiers and highly accurate circuit elements.
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