Metrology measurement and defect inspection steps are ever present in the semiconductor industry in every technology node (see Fig. 4.1). Given the increasing difficulty in manufacturing current- and future-generation chip technologies, process teams increasingly rely on metrology and defectinspection engineers to develop manufacturable processes. A working chip takes months to manufacture and can include as many as 1800 steps in a route (a route is a complete set of steps properly ordered to manufacture a given chip). Chips are typically produced by a particular technology node, which defines the level of technology and complexity used to manufacture the chip. A 65-nm technology node is much less complex than a 22-nm or 14-nm technology node. As mentioned earlier, the number generally indicates the minimum size of the circuitry being printed. Figure 4.1 shows the percentage of the route used by metrology and defect-inspection steps from the 65-nm node to the 14-nm node at IBM and GlobalFoundries. These technology node designations are used internally at IBM but are similar to designations used at other companies. Note that the first three categories of steps shown are for e-beam metrology, inspection, and defect review. A CD-SEM is responsible for dimensional/structural measurements; e-beam review (EBR) is responsible for defect re-detection and classification; and e-beam inspection (EBI) is responsible for physical defect inspection.
Online access to SPIE eBooks is limited to subscribing institutions.