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In replicating an integrated circuit layout during fabrication, the same object shapes are often delineated numerous times. Because of unavoidable variabilities of a manufacturing process, the delineated shapes are generally different from the nominal shapes and from one another. This variability should be kept under the specified tolerance according to which integrated circuits are designed. Too much deviation causes circuit failure. An understanding of the various causes of variation is helpful in devising means to reduce, stabilize, and compensate for the undesirable variation. Although all processing steps (such as deposition, lithography, etching, and chemical-mechanical polishing) contribute to patterning nonuniformity, we focus on variabilities arising from optical imaging, since, with both layout shapes and image tolerance shrinking rapidly compared with λ 0 ∕NA , control of image variabilities is of increasing concern. Lithography becomes more difficult with decreasing k 1 and k 1half-pitch .
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