Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework

Shahzad Ahmad Butt; Stéphane Mancini; Frédéric Rousseau; Luciano Lavagno

doi:10.1117/1.JEI.23.5.053012

23 September 2014 Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework

Shahzad Ahmad Butt, Stéphane Mancini, Frédéric Rousseau, Luciano Lavagno

Author Affiliations +

Journal of Electronic Imaging, Vol. 23, Issue 5, 053012 (September 2014). https://doi.org/10.1117/1.JEI.23.5.053012

Abstract

The pseudo-log image transform belongs to a class of image processing kernels that generate memory references which are nonlinear functions of loop indices. Due to the nonlinearity of the memory references, the usual design methodologies do not allow efficient hardware implementation for nonlinear kernels. For optimized hardware implementation, these kernels require the creation of a customized memory hierarchy and efficient data/memory management strategy. We present the design and real-time hardware implementation of a pseudo-log image transform IP (hardware image processing engine) using a memory management framework. The framework generates a controller which efficiently manages input data movement in the form of tiles between off-chip main memory, on-chip memory, and the core processing unit. The framework can jointly optimize the memory hierarchy and the tile computation schedule to reduce on-chip memory requirements, to maximize throughput, and to increase data reuse for reducing off-chip memory bandwidth requirements. The algorithmic C++ description of the pseudo-log kernel is profiled in the framework to generate an enhanced description with a customized memory hierarchy. The enhanced description of the kernel is then used for high-level synthesis (HLS) to perform architectural design space exploration in order to find an optimal implementation under given performance constraints. The optimized register transfer level implementation of the IP generated after HLS is used for performance estimation. The performance estimation is done in a simulation framework to characterize the IP with different external off-chip memory latencies and a variety of data transfer policies. Experimental results show that the designed IP can be used for real-time implementation and that the generated memory hierarchy is capable of feeding the IP with a sufficiently high bandwidth even in the presence of long external memory latencies.

Citation Download Citation

Shahzad Ahmad Butt, Stéphane Mancini, Frédéric Rousseau, and Luciano Lavagno "Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework," Journal of Electronic Imaging 23(5), 053012 (23 September 2014). https://doi.org/10.1117/1.JEI.23.5.053012

Published: 23 September 2014

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available