1 October 2010 Roughness characterization in the frequency domain and linewidth roughness mitigation with post-lithography processes
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Abstract
A previously developed linewidth roughness analysis technique is used to characterize post-lithography process roughness reduction in the frequency domain. Post-lithography processes are likely to be required to reach the International Technology Roadmap for Semiconductors roughness specifications for the 32-nm and 22-nm technological nodes. The aim of these processes is to reduce 3 linewidth roughness after etch without dramatic changes in critical dimensions. Various techniques are discussed: in-track chemical processes, ion-beam sputtering, and thermal and plasma treatments-each technique manifests a characteristic smoothing, reducing roughness up to 34%. Exploiting roughness mitigation at different frequencies, our target is to determine whether 50% 3 linewidth roughness reduction after etch is feasible.
©(2010) Society of Photo-Optical Instrumentation Engineers (SPIE)
Alessandro Vaglio-Pret, Roel Gronheid, and Philippe Foubert "Roughness characterization in the frequency domain and linewidth roughness mitigation with post-lithography processes," Journal of Micro/Nanolithography, MEMS, and MOEMS 9(4), 041203 (1 October 2010). https://doi.org/10.1117/1.3494614
Published: 1 October 2010
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CITATIONS
Cited by 16 scholarly publications.
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KEYWORDS
Etching

Semiconducting wafers

Critical dimension metrology

Photoresist processing

Ion beams

Sputter deposition

Standards development

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