1 January 1992 High-quality image processing architecture for facsimiles
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A total and coherent image processing architecture for G3/G4/ISDN facsimiles is proposed that features high-quality multi-level processing by means of correlative area scanning and a software-oriented processing architecture. This image processing LSI controller includes a resolution converter and error diffusion halftone processing circuits in 4000 gates. A semi-superfine scanning mode is evaluated, which will be adopted as a new CCITT G3 optional mode.
Keisuke Nakashima, Keisuke Nakashima, Shin'ichi Shinoda, Shin'ichi Shinoda, Yasuyuki Kojima, Yasuyuki Kojima, Yasuro Hori, Yasuro Hori, Toshiaki Nakamura, Toshiaki Nakamura, Noboru Suemori, Noboru Suemori, } "High-quality image processing architecture for facsimiles," Journal of Electronic Imaging 1(1), (1 January 1992). https://doi.org/10.1117/12.55179 . Submission:

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