1 October 1992 High-speed hardware architecture for high-definition videotex system
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Abstract
A high-speed hardware architecture for an experimental high-definition videotex system for a broadband integrated services digital network is introduced. The key technologies required are high-speed protocol processing, high-speed data transfer, and high-speed picture readout from disks. High-speed protocol processing using a newly developed virtual memory copy, content rearrangement memory, two-bus architecture, and simultaneous editing and analyzing allows a requested 6-MB picture to be displayed within 3 s.
Mitsuru Maruyama, Mitsuru Maruyama, Hiroaki Sakamoto, Hiroaki Sakamoto, Yutaka Ishibashi, Yutaka Ishibashi, Kazutoshi Nishimura, Kazutoshi Nishimura, } "High-speed hardware architecture for high-definition videotex system," Journal of Electronic Imaging 1(4), (1 October 1992). https://doi.org/10.1117/12.60922 . Submission:
JOURNAL ARTICLE
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