1 January 2001 Real-time field programmable gate array architecture for computer vision
Author Affiliations +
J. of Electronic Imaging, 10(1), (2001). doi:10.1117/1.1329341
Abstract
This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and it is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on dedicated very-large-scale-integrated devices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed.
Miguel Arias-Estrada, Cesar Torres-Huitzil, "Real-time field programmable gate array architecture for computer vision," Journal of Electronic Imaging 10(1), (1 January 2001). http://dx.doi.org/10.1117/1.1329341
JOURNAL ARTICLE
8 PAGES


SHARE
KEYWORDS
Image processing

Field programmable gate arrays

Computer architecture

Edge detection

Detection and tracking algorithms

Convolution

Computer vision technology

RELATED CONTENT

Some Zoological Studies With Image Intensifiers
Proceedings of SPIE (March 01 1974)
Compact prototype one-step Ultragram printer
Proceedings of SPIE (September 17 1993)
Searching strain field parameters by genetic algorithms
Proceedings of SPIE (September 10 2007)
Accelerating sub-pixel marker segmentation using GPU
Proceedings of SPIE (February 04 2009)

Back to Top