1 January 2002 New hardware memory management architecture for fast neighborhood access based on graph analysis
Author Affiliations +
J. of Electronic Imaging, 11(1), (2002). doi:10.1117/1.1426385
A large number of image processing algorithms are based on neighborhood operations, meaning that several pixels must be accessed for one pixel value computation. This memory overhead is the bottleneck of many image processing systems. Some well known pipeline structures help to reduce this overhead when predictable scanning schemes are used. Unfortunately, it turns out that they cannot cope with unpredictable image scanning which has proved to be very efficient in the implementation of certain operators. This paper addresses a new memory management structure which enables parallel neighborhood access even when random scanning is used. It is based on a neighborhood graph analysis. We show that a graph coloration approach enables optimal memory partitioning to be determined. The most common connectivity graphs are investigated and a detailed description of a suitable structure for the square grid is given. This architecture is not dedicated to any particular algorithm and can be used whenever neighborhood access is an issue. The architecture implementation is described and we show that no complex hardware is required. Timing performance is discussed and an application example is given.
Dominique Noguet, Michel Ollivier, "New hardware memory management architecture for fast neighborhood access based on graph analysis," Journal of Electronic Imaging 11(1), (1 January 2002). http://dx.doi.org/10.1117/1.1426385

Image processing


Content addressable memory

Raster graphics


Field programmable gate arrays

Mathematical morphology


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