Median filtering has proved an effective way to remove impulse noise while preserving rapid signal changes. A classic general purpose median filter is based on a bubble sort approach. We present a novel bit-level algorithm that is readily scalable and very compact. The basis of the algorithm is similar to that of Quicksort, and is based on a bit voter (BV) block. The work also extends the basic BV algorithm to include weighted median and ranked order median filtering. The median finding unit, whose inputs are the N pixel values to sort, has an O(N) hardware complexity compared to an O(N2) complexity for an equivalent unit using bubble sort. The novel algorithm has been implemented on a Xilinx Spartan XCS30XL-4 FPGA chip. For comparison purposes, we also present an FPGA implementation of an existing triple input sorter based algorithm (TIS), which is an optimized version of the bubble sort algorithm for the special case of a 3×3 window size. The BV median finding unit occupies 15 configurable logic blocks (CLBs) only, whereas TIS occupies 60 CLBs. For PAL video (720×576 images of 8-bit/pixel), comparative timings show that BV can operate at 26 frames/sec (fps), while TIS can achieve 33 fps. Thus, both algorithms can achieve real-time performance, and BV is the more compact.