1 July 2003 Using field programmable gate arrays to scale up the speed of holographic video computation
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Abstract
The generation of computer-generated holographic fringes for real-time holographic video (holovideo) display is very computation-intensive, requiring the development of such special systems as the Massachusetts Institute of Technology (MIT) Media Lab's "Holo-Chidi" system, which can generate and display holovideo at video rates. The Holo-Chidi system is made of two sets of cards—the set of processor cards and the set of video concentrator cards (VCCs). The processor cards are used for hologram computation, data archival/retrieval from a host system, and higher level control of the VCCs. The VCC formats compute holographic data from multiple hologram computing processor cards, converting the digital data to analog form to feed the acousto-optic modulators of the Media Lab's "MarkII" holographic display system. The generation of the holographic fringes from the 3-D numerical description of a scene takes place inside field-programmable gate arrays (FPGAs) resident in the processor card. These large FPGAs employ several superposition processing pipelines, all working in parallel to generate the fringes of the hologram frame. With nine processor boards, there are the equivalent of about 288 superposition "processors" generating the fringes simultaneously. A Holo-Chidi system with three VCCs has enough frame buffering capacity to hold up to 32 36-Mbyte hologram frames at a time. Precomputed holograms can also be loaded into the VCC from a host computer through the low-speed universal serial bus (USB) port.
© (2003) Society of Photo-Optical Instrumentation Engineers (SPIE)
Thomas A. Nwodoh, Thomas A. Nwodoh, } "Using field programmable gate arrays to scale up the speed of holographic video computation," Journal of Electronic Imaging 12(3), (1 July 2003). https://doi.org/10.1117/1.1579488 . Submission:
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