1 January 2007 New systolic array processor architecture for simultaneous discrete convolution of an image plane with multiple filter coefficient sets
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Abstract
A new high-performance scalable systolic array processor architecture module for implementation of the two-dimensional discrete convolution algorithm on an (i×j) pixel input image plane (IP) using an (n×n) filter coefficient (FC) plane is first presented. The module generates one convoluted output image (OI) plane pixel per system clock cycle for an (n×n) FC plane using a level of r hardware resources. Second, the architecture is extended in a modular scalable manner to allow simultaneous convolution of a single IP, with k different (n×n) FC planes, such that k convoluted OI plane pixels are generated each system clock cycle, utilizing less than (k*r) hardware resources. The new convolution architecture may be implemented to an ASIC or programmable logic device (PLD) platform. Results of synthesizing and implementing the proposed architecture are shown, illustrating the scalability of the new convolution architecture relative to k. Results from postimplementation virtual hardware prototype simulation testing and from testing a PLD-based experimental hardware prototype are shown that validate correct functional and performance operation of the new convolution architecture module.
© (2007) Society of Photo-Optical Instrumentation Engineers (SPIE)
Albert T. Wong, James Robert Heath, Michael E. Lhamon, "New systolic array processor architecture for simultaneous discrete convolution of an image plane with multiple filter coefficient sets," Journal of Electronic Imaging 16(1), 013014 (1 January 2007). https://doi.org/10.1117/1.2710469 . Submission:
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