1 July 2010 Field-programmable gate array-based hardware architecture for image processing with complementary metal-oxide-semiconductor image sensor
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Abstract
We present a field-programmable gate array (FPGA)-based hardware architecture for image processing as well as novel algorithms for fast autoexposure control and color filter array (CFA) demosaicing utilizing a CMOS image sensor (CIS). The proposed hardware architecture includes basic color processing functions of black-level correction, noise reduction, autoexposure control, auto-white-balance adjustment, CFA demosaicing, and gamma correction while applying advanced peripheral bus architecture to implement the hardware architecture. The speed of traditional autoexposure control algorithms to reach a proper exposure level is so slow that it is necessary to develop a fast autoexposure control method. Based on the optical-electrical characteristics of the CIS, we present a fast auto-exposure-control algorithm that can guarantee speed and accuracy. To ensure the peak SNR performance of the demosaiced images of the CIS and reduce the computational cost at the same time, the proposed demosaicing algorithm improves on the adaptive edge-sensitive algorithm and the fuzzy assignment algorithm. The experimental results show that the proposed hardware architecture works well on the FPGA development board and produces better quality images.
© (2010) Society of Photo-Optical Instrumentation Engineers (SPIE)
Zhiwei Ge, Suying Yao, Jiangtao Xu, "Field-programmable gate array-based hardware architecture for image processing with complementary metal-oxide-semiconductor image sensor," Journal of Electronic Imaging 19(3), 033014 (1 July 2010). https://doi.org/10.1117/1.3483904 . Submission:
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