18 June 2013 System of a programmable-chip-based image-processing system
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Recent advances in semiconductor technology have made it possible to integrate an entire system including processors, memory, and other system units into a single programmable chip [a field programmable gate array (FPGA)]. These configurations, called system on a programmable chip (SOPC), have the advantage of being designed and implemented quicker than traditional technologies and are relatively cheap to produce for low volume applications. One processor-intensive application, which is ideal for SOPC technology, is that of image processing where there is a repeated application of operations on the two-dimensional data. We present the results of research that investigate the use of SOPC technology in building a real-time image-processing system with the capability of performing video acquisition, image processing, and image display. In order to solve the complex on-chip data communication, while not degrading the transfer speed of large amounts of video data, a novel and effective bus arbitration solution called “simultaneously multimastering Avalon streaming transfer with peripheral-controlled waitrequest” is developed. Rather than using the software approach to initialize direct memory access (DMA) like transfers, this solution takes advantage of the FPGA hardware resources to perform bus arbitration and hence increase system efficiency.
© 2013 SPIE and IS&T
Fan Wu, Fan Wu, Jeremy S. Smith, Jeremy S. Smith, Andrew J. Tickle, Andrew J. Tickle, Qiang Huang, Qiang Huang, } "System of a programmable-chip-based image-processing system," Journal of Electronic Imaging 22(2), 023026 (18 June 2013). https://doi.org/10.1117/1.JEI.22.2.023026 . Submission:


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