9 February 2015 Real-time high-resolution downsampling algorithm on many-core processor for spatially scalable video coding
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The progression toward spatially scalable video coding (SVC) solutions for ubiquitous endpoint systems introduces challenges to sustain real-time frame rates in downsampling high-resolution videos into multiple layers. In addressing these challenges, we put forward a hardware accelerated downsampling algorithm on a parallel computing platform. First, we investigate the principal architecture of a serial downsampling algorithm in the Joint-Scalable-Video-Model reference software to identify the performance limitations for spatially SVC. Then, a parallel multicore-based downsampling algorithm is studied as a benchmark. Experimental results for this algorithm using an 8-core processor exhibit performance speedup of 5.25 × against the serial algorithm in downsampling a quantum extended graphics array at 1536p video resolution into three lower resolution layers (i.e., Full-HD at 1080p, HD at 720p, and Quarter-HD at 540p). However, the achieved speedup here does not translate into the minimum required frame rate of 15 frames per second (fps) for real-time video processing. To improve the speedup, a many-core based downsampling algorithm using the compute unified device architecture parallel computing platform is proposed. The proposed algorithm increases the performance speedup to 26.14 × against the serial algorithm. Crucially, the proposed algorithm exceeds the target frame rate of 15 fps, which in turn is advantageous to the overall performance of the video encoding process.
© 2015 SPIE and IS&T
Adamu M. Buhari, Adamu M. Buhari, Huo-Chong Ling, Huo-Chong Ling, Vishnu M. Baskaran, Vishnu M. Baskaran, KokSheik Wong, KokSheik Wong, } "Real-time high-resolution downsampling algorithm on many-core processor for spatially scalable video coding," Journal of Electronic Imaging 24(1), 013025 (9 February 2015). https://doi.org/10.1117/1.JEI.24.1.013025 . Submission:


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