High-throughput sample adaptive offset hardware architecture for high-efficiency video coding

Wei Zhou; Chang Yan; Jingzhi Zhang; Zhou Xin

doi:10.1117/1.JEI.27.2.023035

27 April 2018 High-throughput sample adaptive offset hardware architecture for high-efficiency video coding

Wei Zhou, Chang Yan, Jingzhi Zhang, Zhou Xin

Author Affiliations +

Journal of Electronic Imaging, Vol. 27, Issue 2, 023035 (April 2018). https://doi.org/10.1117/1.JEI.27.2.023035

Abstract

A high-throughput hardware architecture for a sample adaptive offset (SAO) filter in the high-efficiency video coding video coding standard is presented. First, an implementation-friendly and simplified bitrate estimation method of rate-distortion cost calculation is proposed to reduce the computational complexity in the mode decision of SAO. Then, a high-throughput VLSI architecture for SAO is presented based on the proposed bitrate estimation method. Furthermore, multiparallel VLSI architecture for in-loop filters, which integrates both deblocking filter and SAO filter, is proposed. Six parallel strategies are applied in the proposed in-loop filters architecture to improve the system throughput and filtering speed. Experimental results show that the proposed in-loop filters architecture can achieve up to 48% higher throughput in comparison with prior work. The proposed architecture can reach a high-operating clock frequency of 297 MHz with TSMC 65-nm library and meet the real-time requirement of the in-loop filters for 8 K × 4 K video format at 132 fps.

Citation Download Citation

Wei Zhou, Chang Yan, Jingzhi Zhang, and Zhou Xin "High-throughput sample adaptive offset hardware architecture for high-efficiency video coding," Journal of Electronic Imaging 27(2), 023035 (27 April 2018). https://doi.org/10.1117/1.JEI.27.2.023035

Received: 8 September 2017; Accepted: 10 April 2018; Published: 27 April 2018

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