4 May 2018 Accelerating image convolution filtering algorithms on integrated CPU–GPU architectures
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Convolution filtering is one of the most important algorithms in image processing. It is data-intensive, especially when dealing with high-definition images. Most previous studies on accelerating convolution computation in parallel focus on the use of graphics processing units (GPUs), whereas the central processing units (CPUs) always play the role of host to manage the data buffer and control flow. However, recent CPU architectures have seen significant modifications to parallel data computing capabilities, and the trend of integrating the CPU and GPU on a single chip is on a rise. We propose an approach to accelerate convolution filtering on the heterogeneous architecture of integrated CPU–GPU. We exploit the parallel processing power of vector instructions on a CPU and make it collaboratively function with the on-chip GPU. Two task assignment methods, static and dynamic task partitioning, are proposed for CPU–GPU collaboration. We evaluate our approach with images and filters of different sizes. The experimental results demonstrate that we can achieve 146 GFLOP/s at best using a quad-core CPU and the performance is 2.5 to 4.8 times faster than that of the single-GPU version of the OpenCV library. We also obtain 90 times speedup over the single-threaded CPU version. The results demonstrate that the proposed algorithm is efficient.
© 2018 SPIE and IS&T
Yi Zhou, Yi Zhou, Fazhi He, Fazhi He, Yimin Qiu, Yimin Qiu, } "Accelerating image convolution filtering algorithms on integrated CPU–GPU architectures," Journal of Electronic Imaging 27(3), 033002 (4 May 2018). https://doi.org/10.1117/1.JEI.27.3.033002 . Submission: Received: 9 September 2017; Accepted: 13 April 2018
Received: 9 September 2017; Accepted: 13 April 2018; Published: 4 May 2018

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