Open Access
12 August 2013 Contact hole shrink process using graphoepitaxial directed self-assembly lithography
Yuriko Seino, Hiroki Yonemitsu, Hironobu Sato, Masahiro Kanno, Hirokazu Kato, Katsutoshi Kobayashi, Ayako Kawanishi, Tsukasa Azuma, Makoto Muramatsu, Seiji Nagahara, Takahiro Kitano, Takayuki Toshima
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Abstract
A contact hole shrink process using directed self-assembly lithography (DSAL) for sub-30 nm contact hole patterning is reported on. DSAL using graphoepitaxy and poly (styrene-block-methyl methacrylate) (PS-b -PMMA) a block copolymer (BCP) was demonstrated and characteristics of our process are spin-on-carbon prepattern and wet development. Feasibility of DSAL for semiconductor device manufacturing was investigated in terms of DSAL process window. Wet development process was optimized first; then critical dimension (CD) tolerance of prepattern was evaluated from three different aspects, which are DSA hole CD, contact edge roughness (CER), and hole open yield. Within 70+/−5  nm hole prepattern CD, 99.3% hole open yield was obtained and CD tolerance was 10 nm. Matching between polymer size and prepattern size is critical, because thick PS residual layer appears at the hole bottom when the prepattern holes are too small or too large and results in missing holes after pattern transfer. We verified the DSAL process on a 300-mm wafer at target prepattern CD and succeeded in patterning sub-30 nm holes on center, middle, and edge of wafer. Average prepattern CD of 72 nm could be shrunk uniformly to DSA hole pattern of 28.5 nm. By the DSAL process, CD uniformity was greatly improved from 7.6 to 1.4 nm, and CER was also improved from 3.9 to 0.73 nm. Those values represent typical DSAL rectification characteristics and are significant for semiconductor manufacturing. It is clearly demonstrated that the contact hole shrink using DSAL is a promising patterning method for next-generation lithography.
© The Authors. Published by SPIE under a Creative Commons Attribution 3.0 Unported License. Distribution or reproduction of this work in whole or in part requires full attribution of the original publication, including its DOI.
Yuriko Seino, Hiroki Yonemitsu, Hironobu Sato, Masahiro Kanno, Hirokazu Kato, Katsutoshi Kobayashi, Ayako Kawanishi, Tsukasa Azuma, Makoto Muramatsu, Seiji Nagahara, Takahiro Kitano, and Takayuki Toshima "Contact hole shrink process using graphoepitaxial directed self-assembly lithography," Journal of Micro/Nanolithography, MEMS, and MOEMS 12(3), 033011 (12 August 2013). https://doi.org/10.1117/1.JMM.12.3.033011
Published: 12 August 2013
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CITATIONS
Cited by 47 scholarly publications and 2 patents.
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KEYWORDS
Directed self assembly

Critical dimension metrology

Semiconducting wafers

Lithography

Polymethylmethacrylate

System on a chip

Semiconductor manufacturing

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