Abstract
Although a number of factors relating to lithography and material stacking have been investigated to realize hotspot-free wafer images, hotspots are often still found on wafers. For the 22-nm technology node and beyond, the detection and repair of hotspots with lithography simulation models is extremely time-consuming. Thus, hotspots represent a critical problem that not only causes delays to process development but also represents lost business opportunities. In order to solve the time-consumption problem of hotspots, this paper proposes a new method of hotspot prevention and detection using an image recognition technique based on higher-order local autocorrelation, which is adopted to extract geometrical features from a layout pattern. To prevent hotspots, our method can generate proper verification patterns to cover the pattern variations within a chip layout to optimize the lithography conditions. Moreover, our method can realize fast hotspot detection without lithography simulation models. Obtained experimental results for hotspot prevention indicated excellent performance in terms of the similarity between generated proposed patterns and the original chip layout patterns, both geometrically and optically. Moreover, the proposed hotspot detection method could achieve turn-around time reductions of <95% for just one CPU, compared to the conventional simulation-based approach, without accuracy losses.
