29 January 2014 Macroinspection methodology for through silicon via array in three-dimensional integrated circuit
Author Affiliations +
Abstract
We are developing a new macroinspection technology for through silicon via (TSV) process wafers. We present new simulation results obtained with a fine TSV model and new optics. The optical system includes not only diffraction optics, but also polarization optics, by which we can detect changes in the profile (cross-sectional shape) of repeated patterns by detecting changes in the polarization status of reflected light. We confirmed the performance of the methodology by optical simulation using a model of via patterns with 1 μm diameter and 10 μm depth as a typical intermediate-interconnect-level TSV.
© 2014 Society of Photo-Optical Instrumentation Engineers (SPIE)
Yoshihiko Fujimori, Takashi Tsuto, Hiroyuki Tsukamoto, Kazuya Okamoto, Kyoichi Suwa, "Macroinspection methodology for through silicon via array in three-dimensional integrated circuit," Journal of Micro/Nanolithography, MEMS, and MOEMS 13(1), 011204 (29 January 2014). https://doi.org/10.1117/1.JMM.13.1.011204 . Submission:
JOURNAL ARTICLE
8 PAGES


SHARE
Back to Top