27 August 2014 Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure
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Abstract
In this work, we have investigated the evolution of line roughness from the photoresist (PR) to the poly-silicon gate etch based on the composite SiO2 /Si3 N4 /SiO2 (ONO) multilayer hard mask structure using a capacitively coupled plasma etcher. A severe line roughness could be observed during gate patterning when the PR pattern was directly transferred into the ONO hard mask. Then, the formation mechanisms of line roughness were the results of the effects of decomposed oxygen radical generated from the SiO 2 mask because of ion bombardment and the rough surface morphology of poly-silicon that accelerates the etching of both the hard mask and the PR sidewalls by reflected ions. We found that a combination of an amorphous silicon (α -Si) capping layer and amorphous Si gate could effectively reduce the strong dependence of hard mask etch on PR and ions reflection effect from rough surface morphology of poly-silicon. Finally, our results have shown that the gate pattern with a fairly smooth line, without deformation, and with the gate length of 29 nm and the line width roughness of 3.4 nm can be achieved.
© 2014 Society of Photo-Optical Instrumentation Engineers (SPIE)
Lingkuan Meng, Lingkuan Meng, Xiaobin He, Xiaobin He, Chunlong Li, Chunlong Li, Junjie Li, Junjie Li, Peizhen Hong, Peizhen Hong, Junfeng Li, Junfeng Li, Chao Zhao, Chao Zhao, Jiang Yan, Jiang Yan, } "Transistor gate line roughness formation and reduction in sub-30-nm gate patterning using multilayer hard mask structure," Journal of Micro/Nanolithography, MEMS, and MOEMS 13(3), 033010 (27 August 2014). https://doi.org/10.1117/1.JMM.13.3.033010 . Submission:
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