16 September 2014 Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
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Abstract
A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables the possibility to objectively compare the lithography quality of different layout design implementations. Moreover, we propose a pattern construct classifier to reduce the set of lithography simulations necessary to estimate the litho degradation. The application of the yield model is demonstrated for different layout configurations showing that a certain degree of layout regularity improves the parametric yield and increases the number of good dies per wafer.
© 2014 Society of Photo-Optical Instrumentation Engineers (SPIE)
Sergio Gómez, Sergio Gómez, Francesc Moll, Francesc Moll, Joan Mauricio, Joan Mauricio, } "Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations," Journal of Micro/Nanolithography, MEMS, and MOEMS 13(3), 033016 (16 September 2014). https://doi.org/10.1117/1.JMM.13.3.033016 . Submission:
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