5 March 2015 Gate double patterning strategies for 10-nm node FinFET devices
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Abstract
Amorphous silicon (a-Si) gates with a length of 20 nm have been obtained in a “line & cut” double patterning process. The first pattern was printed with extreme ultraviolet photoresist (PR) and had a critical dimension (CD) close to 30 nm, which imposed a triple challenge on the etch: limited PR budget, high line width roughness, and significant CD reduction. Combining a plasma pre-etch treatment of the PR with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.
© 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)
Hubert Hody, Vasile Paraschiv, David Hellin, Tom Vandeweyer, Guillaume Boccardi, Kaidong Xu, "Gate double patterning strategies for 10-nm node FinFET devices," Journal of Micro/Nanolithography, MEMS, and MOEMS 14(1), 014504 (5 March 2015). https://doi.org/10.1117/1.JMM.14.1.014504 . Submission:
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