25 February 2016 Architectural strategies in standard-cell design for the 7 nm and beyond technology node
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Abstract
Standard-cell design and characterization are presented for 7-nm CMOS platform technology targeting low-power and high-performance applications with the tightest contacted poly pitch of 42 nm and a metallization pitch of 32 nm in the FinFET technology. Two standard-cell architectures for 7 nm, a 9-track library and a 7.5-track library have been designed, introducing an extra middle-of-line layer to enable an efficient layout of the 7.5-track cells. The 7.5-track cells are on average smaller than the 9-track cells. With the strict design constraints imposed by self-aligned quadruple patterning and self-aligned double patterning, careful design and technology co-optimization is performed.
© 2016 Society of Photo-Optical Instrumentation Engineers (SPIE)
Syed Muhammad Yasser Sherazi, Syed Muhammad Yasser Sherazi, Bharani Chava, Bharani Chava, Peter Debacker, Peter Debacker, Marie Garcia Bardon, Marie Garcia Bardon, Pieter Schuddinck, Pieter Schuddinck, Farshad Firouzi, Farshad Firouzi, Praveen Raghavan, Praveen Raghavan, Abdelkarim Mercha, Abdelkarim Mercha, Diederik Verkest, Diederik Verkest, Julien Ryckaert, Julien Ryckaert, } "Architectural strategies in standard-cell design for the 7 nm and beyond technology node," Journal of Micro/Nanolithography, MEMS, and MOEMS 15(1), 013507 (25 February 2016). https://doi.org/10.1117/1.JMM.15.1.013507 . Submission:
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