In aggressively scaled devices, FinFET technology has become more prone to line-edge roughness (LER) induced threshold voltage variability. To explain this challenge, all possible LER-induced fin shape variabilities in spacer-defined patterning (i.e., correlated LER) and resist-defined patterning (i.e., uncorrelated LER) technology have been investigated for 14-nm underlap FinFET using 3-D numerical simulations. All LER-induced
variabilities are analyzed in the presence of other intrinsic variability sources, such as random dopant fluctuation (RDF), work function variation (WFV), and oxide thickness variation (OTV). This study reveals that the percentage threshold voltage (
) fluctuations of combined effects (RDF, WFV, and OTV) in spacer-defined and resist-defined FinFETs with respect to rectangular FinFET are 2.88% and 8.76%, respectively.