19 March 2018 Device- and circuit-level variability due to random discrete dopant in resist- and spacer-defined nanoscale FinFETs
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Abstract
In current CMOS technology, parameter variations are playing a vital role in limiting the benefits of downscaling, especially in the nanodomain. This work presents the investigation of random dopant fluctuation (RDF) in several possible line-edge roughness (LER)-induced fin shapes of spacer- (i.e., correlated LER) and resist- (i.e., uncorrelated LER) defined patterning techniques for a 14-nm FinFET structure. The three-dimensional (3-D) technology computer-aided design simulation on a large statistical ensemble has been carried out to analyze the impact of the RDF on various device parameters such as threshold voltage, drive current, off current, and drain-induced barrier lowering. It is observed that the impact of RDF on electrical parameters mainly depends on the fin shape and is dominant in all resist-defined FinFET structures. It is also found that the impact of RDF can diminish significantly using the spacer-defined patterning technique. Further, the impact of RDF in spacer- and resist-defined FinFET structures has been investigated for noise margins of 6-T static random access memories (SRAM). It is concluded that random dopant variations in SRAM performance offer better immunity in the case of spacer-defined FinFETs compared with resist-defined FinFETs.
© 2018 Society of Photo-Optical Instrumentation Engineers (SPIE)
Rituraj Singh Rathore, Ashwani K. Rana, "Device- and circuit-level variability due to random discrete dopant in resist- and spacer-defined nanoscale FinFETs," Journal of Micro/Nanolithography, MEMS, and MOEMS 17(1), 013507 (19 March 2018). https://doi.org/10.1117/1.JMM.17.1.013507 . Submission: Received: 9 May 2017; Accepted: 20 February 2018
Received: 9 May 2017; Accepted: 20 February 2018; Published: 19 March 2018
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