11 February 2019 Analyzing wafer leveling data from high-volume manufacturing to identify the sources of inline defectivity
Fauzia Khatkhatay
Author Affiliations +
Abstract
Sampling-limited inline defect inspections may fall short in the timely detection of new defects or small baseline populations, especially when the defects have unique spatial orientations. In such cases, it may be beneficial to also consider fault detection and classification signals from unit process modules. Lithography scanners determine the optimal focus position for a wafer by a process called leveling. This work uses a defect analysis approach to examine focus spot data, a litho tool level signal extracted from wafer leveling, and to isolate the sources of inline defectivity from four consecutive front-end-of-line litho steps in a high-volume manufacturing fab. The scope is broadened to examine all litho layers from the same technology node that process on the same tool platform. This work highlights the immense potential of mining focus spot data as a powerful complement to inline defect monitoring.
© 2019 Society of Photo-Optical Instrumentation Engineers (SPIE) 1932-5150/2019/$25.00 © 2019 SPIE
Fauzia Khatkhatay "Analyzing wafer leveling data from high-volume manufacturing to identify the sources of inline defectivity," Journal of Micro/Nanolithography, MEMS, and MOEMS 18(1), 014001 (11 February 2019). https://doi.org/10.1117/1.JMM.18.1.014001
Received: 16 October 2018; Accepted: 17 January 2019; Published: 11 February 2019
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KEYWORDS
Semiconducting wafers

Signal processing

Manufacturing

Front end of line

High volume manufacturing

Back end of line

Signal detection

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