1 April 2004 Optimization of sub-100-nm designs for mask cost reduction
Author Affiliations +
Abstract
For sub-100 nm integrated circuit (IC) technologies, many of the factors that affect the cost of photomasks, the cost of material, of the writing process, of the develop/etch process, and of inspection, are increasing by an order of magnitude per generation. In order to mitigate the impact of that increase on the return on investment of new IC products, mask shop deliverables such as yield or alignment with technology requirements need to reach new quality. This work focuses on cost containment of the mask by optimally utilizing existing reticle technology to meet device requirements at the product level. We first compare the increase of mask cost with that of other manufacturing equipment categories, and discuss their dependence on layer properties and how to control increasing costs. We then propose use of a new procedure called integrated simulation (optical combined with electrical) to estimate the impact of the mask critical dimension (CD) budget on transistor performance on the local scale (cell level) and global scale (die level). In the process, at the cell level, simulated aerial images of metal-oxide-semiconductor field-effect transistor channels are used to evaluate the parametric data dependence on the optical proximity effects and correction features at the mask grade assumed. At the die level, statistical distribution of device parameters in the die is derived to estimate the parametric yield impacted by mask CD variation. We also discuss how integrated simulation can help in resolving other challenges of advanced reticle manufacturing such as qualification of masks or the generation of dummy patterns.
© (2004) Society of Photo-Optical Instrumentation Engineers (SPIE)
Artur P. Balasinski, "Optimization of sub-100-nm designs for mask cost reduction," Journal of Micro/Nanolithography, MEMS, and MOEMS 3(2), (1 April 2004). https://doi.org/10.1117/1.1668275 . Submission:
JOURNAL ARTICLE
10 PAGES


SHARE
RELATED CONTENT

Mask cost for sub 100 nm technologies stopping a...
Proceedings of SPIE (July 02 2003)
Reliability simulator for improving IC manufacturability
Proceedings of SPIE (September 14 1994)
DUV mask writer for BEOL 90-nm technology layers
Proceedings of SPIE (December 17 2003)
Device analysis a way to reduce patterning cost at...
Proceedings of SPIE (December 06 2004)

Back to Top