It has been a challenge for the lithography process to meet aggressive integrated circuit design rule requirements for 90 nm and upcoming 65 nm technology nodes under low-k1 patterning constraints. The geometric design rules are largely governed by numerical aperture (NA), illumination settings, and optical proximity correction (OPC) for any resolution enhancement technique-applied mask. A set of process feasible design rule criteria is explored based on state-of-the-art microprocessor chip that contains three different types of circuit design-standard library cell (SLC), random logic (RML), and static random access memory (SRAM). The critical design rule criteria to keep higher packing density for SRAM involve: achievable minimum pitch, sufficient area of contact-landing pad, minimum line-end shortening (LES) to ensure poly end-cap and preferably optimum pitch for placement of Scattering BarTM (SB). The goal is to achieve printing of ever-smaller critical dimension (CD) with greater CD uniformity control for RML. SLC should be designed with comparable criteria to both RML and SRAM devices. Hence, the design rule constraints for CD, space, line-end, minimum pitch and SB placement for SLC cell are critically confined. Unlike traditional method of assuming a linear scaling for the design rule set, achievable design rule criteria is explored for very low k1-imaging by simultaneously optimizing NA, illumination settings and OPC (for optimum placement of SB) for a calibrated process. This is done by analyzing CD uniformity control and maximum overlapped process window for critical lines, spaces and line-ends with the respective k1 factor for three types of circuits. A feasible set of design rules for 90 nm node with k1 as low as 0.36 can be obtained using 6% attenuated phase shift mask (attPSM) with 6% exposure latitude at 400 nm of overlapped depth of focus.