In the past, complying with design rules was sufficient to ensure acceptable yields for a design. However, for sub-100-nm designs, this approach tends to create patterns that cannot be reliably printed for a given optical setup, thus leading to hot spots and systematic yield failures. Recent challenges faced by both the design and process communities call for a paradigm shift whereby circuits are constructed from a small set of lithography-friendly patterns that have previously been extensively characterized and ensured to print reliably. We describe the use of a regular design fabric for defining the underlying layout geometries of the circuit. While the direct application of this methodology to the current application-specific integrated circuit (ASIC) design flow would result in unnecessary area and performance penalties, we overcome these penalties via a unique design flow that ensures shape-level regularity by reducing the number of required logic functions as much as possible as part of the top-down design flow. We show that with a small set of Boolean functions and careful selection of lithography-friendly patterns, we not only mitigate but essentially eliminate such penalties. Additionally, we discuss the benefits of using extremely regular designs constructed from a limited set of lithography-friendly patterns not only to improve manufacturability but also to relax the pessimistic constraints defined by design rules. Specifically, we introduce the basis to exploit the regularity in the layout patterns by using “pushed-rules” for logic design, as is commonly done for static random access memory (SRAM). This in turn facilitates a common optical proximity correction (OPC) methodology for logic and SRAM. Moreover, by taking advantage of this newfound manufacturability and predictability of regular circuits, we show that the performance of logic built on regular fabrics can surpass that of seemingly more arbitrarily constructed logic.