According to the International Technology Roadmap for Semiconductors 2008 (http: www.itrs.net) overlay error should be controlled under 12 nm for sub-60-nm memory devices. To meet such a tight requirement, lot-to-lot high-order wafer correction (HOWC) and per-shot correction (PSC) is evaluated for the gate and contact layers of dynamic random access memory. A commercial package is available from scanner makers, such as ASML, Canon, and Nikon. In this study, HOWC is investigated for wafer correction, whereas PSC is considered for scan direction-dependent overlay correction. Experimental results verify 1-3 nm of overlay improvement by applying HOWC. However, the amount of improvement is layer (process) dependent. It turned out that HOWC is not an overall solution. It should be applied carefully for certain process conditions. In addition, if scan direction is different (mixture of up, down, left, right) due to wafer stage routing path, then overlay performance could be degraded. To solve this problem, PSC is also evaluated. Detailed experimental results are discussed.