1 October 2009 Design-specific variation in pattern transfer by via/contact etch process: full-chip analysis
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Abstract
A novel model-based algorithm provides a capability to control full-chip design-specific variation in pattern transfer caused by via/contact etch (VCE) processes. This physics-based algorithm is capable of detecting and reporting etch hot spots based on the fabrication-defined thresholds of acceptable variations in critical dimension (CD) of etched shapes. It can be used also as a tool for etch process optimization to capture the impact of a variety of patterns presented in a particular design. A realistic set of process parameters employed by the developed model allows using this novel VCE electronic design automation tool for design-aware process optimization in addition to the "standard" process-aware design optimization.
© (2009) Society of Photo-Optical Instrumentation Engineers (SPIE)
Valeriy Sukharev, Valeriy Sukharev, Ara Markosian, Ara Markosian, Armen Kteyan, Armen Kteyan, Levon Manukyan, Levon Manukyan, Nikolay Khachatryan, Nikolay Khachatryan, Jun-Ho Choy, Jun-Ho Choy, Hasmik Lazaryan, Hasmik Lazaryan, Henrik Hovsepyan, Henrik Hovsepyan, Seiji Onoue, Seiji Onoue, Takuo Kikuchi, Takuo Kikuchi, Tetsuya Kamigaki, Tetsuya Kamigaki, } "Design-specific variation in pattern transfer by via/contact etch process: full-chip analysis," Journal of Micro/Nanolithography, MEMS, and MOEMS 8(4), 043007 (1 October 2009). https://doi.org/10.1117/1.3268422 . Submission:
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