1 January 2010 22-nm-node technology active-layer patterning for planar transistor devices
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Abstract
As the semiconductor device size shrinks without a concomitant increase of numerical aperture (NA) and refractive index of the immersion fluid, printing 22-nm-technology devices presents challenges in resolution. Therefore, aggressive integration of a resolution enhancement technique (RET), design for manufacturability (DFM), and layer-specific lithographic process development are strongly required in 22-nm-technology lithography. We show patterning of an active layer of a 22-nm-node planar logic transistor device, and discuss achievements and challenges. Key issues identified include printing tight pitches, isolated trench, and 2-D features while maintaining a large lithographic process window across the chip while scaling down the cell size. Utilizing NA=1.2, printing of the static random access memory (SRAM) of a cell size of 0.1 µm2 and other critical features across the chip with a process window are demonstrated.
© (2010) Society of Photo-Optical Instrumentation Engineers (SPIE)
Ryoung-Han Kim, Ryoung-Han Kim, Steven J. Holmes, Steven J. Holmes, Scott D. Halle, Scott D. Halle, Vito Dai, Vito Dai, Jason E. Meiring, Jason E. Meiring, Aasutosh D. Dave, Aasutosh D. Dave, Matthew E. Colburn, Matthew E. Colburn, Harry J. Levinson, Harry J. Levinson, } "22-nm-node technology active-layer patterning for planar transistor devices," Journal of Micro/Nanolithography, MEMS, and MOEMS 9(1), 013001 (1 January 2010). https://doi.org/10.1117/1.3302125 . Submission:
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