The objective of this work is to determine a guideline for defining practical overlay metrology requirements for a given design rule. Total measurement uncertainty (TMU) of overlay metrology is defined as the square root of square sum of the following items: the mean of the tool-induced shift (TIS), TIS 3-sigma, dynamic precision, and tool-to-tool matching. The TMU is dependent upon process conditions, so TMU is different by process layer. In this study, the impact of TMU on overlay error correction, which includes process and measurement noise, is investigated in terms of the stability of high-order overlay correction parameters. By evaluating the variation range of correctable parameters as a figure of merit, the corresponding TMU is determined for a given design rule. Utilizing this methodology, we determined that 2 nm of TMU value is the allowable limit for 45 nm of dynamic random access memory (DRAM) half pitch based upon simulation results. Similarly, we recommend 1 nm of TMU for 36 nm of DRAM half pitch. Our methodology is described and our simulation results are discussed.