Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less studied. Contact patterning is one of the critical steps in a state of the art lithography process; meanwhile, design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depends on contact area and shape, larger CER results in significant change in a device current. We first propose a CER model based on the power spectral density function, which is a function of rms edge roughness, correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first dissect the contact with a same distance, and then calculate the effective resistance considering both the shape weighting factor and the distance weighting factor for stress-induced complementary metal-oxide semiconductor (CMOS) cells. Using the results of CER, we analyze the impact of both random CER and systematic variation on the S/D contact resistance, and the device saturation current. Results show that the S/D contact resistance and the device saturation current can vary by as much as 135.7 and 4.9%, respectively.