1 October 2010 Electrical validation of through-process optical proximity correction verification limits
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Abstract
Electrical validation of through process optical proximity correction verification limits in 32-nm process technology is presented. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to subdesign rules to force failure and derive better correlation between electrical and simulated outputs. Some of these subdesign rule designs amplify the failures induced by an exposure tool, such as optical aberrations. Observations in this regard are reported. Sensitivity with respect to dimensions, orientations, and wafer distribution are discussed in detail.
© (2010) Society of Photo-Optical Instrumentation Engineers (SPIE)
Omprakash Jaiswal, Rakesh Kuncha, Taksh Bharat, Vipin Madangarli, Edward W. Conrad, James A. Bruce, Sajan R. Marokkey, "Electrical validation of through-process optical proximity correction verification limits," Journal of Micro/Nanolithography, MEMS, and MOEMS 9(4), 041303 (1 October 2010). https://doi.org/10.1117/1.3514703 . Submission:
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