Quantum-dot cellular automata (QCA) is an evolving technology to design circuits at nanometer levels. Most of the digital systems have an adder integrated in the circuit. Circuits in QCA are implemented using majority gates. Most of the existing adder designs are implemented using majority logic and exclusive-or logic. The circuits in QCA are prone to fabrication defects that can affect the performance of the circuit drastically. Missing cell defect is crucial among them. In this work, the existing gates used to implement the adders are analyzed, and a reliable clock zone full adder is proposed using the better fault tolerant gate. The proposed adder is more reliable since both the Sum and Carry are generated by reliable gates. Missing cell defect analysis and design validation are carried out using QCADesigner. The proposed design has fewer cells and more reliability compared to the designs which have considered reliability as an important factor to design adders.
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