2.1.

Superstrates

Low-cost soda-lime glass was employed as the superstrate in some of the early 10% efficient cells. However, the strain point of this glass is only $\sim 515°\mathrm{C}$ and its optical transmission is $<80\%$ for wavelengths $<450$ and $>700\mathrm{nm}$ , ¹⁵ an issue that can be mitigated by reducing the iron content to or $<200\mathrm{ppm}$ . In fabricating the champion cells, R&D groups often employ more expensive but highly transparent glasses with high strain point. For example, the 16.7% cell employed a thin borosilicate glass and a process temperature that reached 660°C. ¹⁶ Therefore, there is continued effort on the part of suppliers to engineer a high-temperature, high-transparency glass, which is also stronger so that superstrates much thinner than the standard 3.2 mm can be used in module fabrication. ¹⁷ Such superstrates, once available at low cost, are expected to yield higher efficiency, lighter-weight commercial CdTe modules. The above-mentioned 16.7% cell also employed a single-layer antireflective (AR) coating on the glass surface. ¹⁶ A recent study demonstrated that a multilayer AR coating can reduce the weighted average reflection of the glass surface from $\sim 4$ to $\sim 1\%$ within the absorption band of CdTe. ¹⁸ Use of AR coatings in commercial modules requires development of cost-effective and environmentally durable films. Information such as the nature of the glass and the AR coating (if any) has not been disclosed for the recently reported champion devices (see Secs. 2.5 and 4.1). However, it would be reasonable to assume that they employed the best quality glass available and possibly an optimized AR coating.

Another topic that attracted recent attention is luminescent down-shifting, ^{19 – 21} which uses a luminescent down-shifting (LDS) material layer on the cell surface to shift the wavelength of high-energy ( $\lambda <500\mathrm{nm}$ ) photons to values around $\sim 600\mathrm{nm}$ . This approach was shown to increase the current density in cells with relatively poor blue response; however, long-term stability and cost aspects of LDS materials are uncertain. Also, the efficiency improvement provided by this approach would diminish as the blue response of the cells is improved through advances made in optical transmission and/or current collection from the glass/TCO/junction-partner stack.

Although glass is the most economical and proven superstrate material, a thin ( $\sim 7.5\mu \text{m}$ ) transparent polyimide foil was also used to demonstrate a flexible CdTe cell. All the layers in this polyimide/ZnO/CdS/CdTe/back-contact device were processed at temperatures $<450°\mathrm{C}$ and an efficiency of 12.7% (with AR coating) was reported. ²²

2.2.

TCO/Junction-Partner Stack

All high-efficiency CdTe cells utilize a thin HRT film between the TCO and CdS layers. Although a wide range of material options and thicknesses have been used to reach cell efficiencies in the 10 to 15% range, a down-selection of the cell stack and the processing options has emerged, which produces efficiencies $>15\%$ . For high efficiency, the junction is typically formed at temperatures near 600°C, limited by the strain point of the glass and the impurity diffusion from the glass into the CdTe absorber. There is typically a diffusion barrier layer (a thin ${\mathrm{SiO}}_2$ film) at the glass/TCO interface to control such diffusion. The window stack utilizes several index-matched layers to (1) reduce reflection, (2) maximize transmittance, (3) control lateral conductivity for current collection, (4) passivate CdTe and form a low-recombination junction, and (5) serve as a CdTe nucleation surface with high in-plane density, low voiding, and low extended defect CdTe growth. For this, fluorine-doped tin oxide and CTO, both of which are stable at temperatures up to $\sim 620°\mathrm{C}$ , have been employed as TCO layers. Typical TCO films are 0.25 to 0.7 microns thick and exhibit sheet resistance in the 5 to $15\mathrm{ohm}/\mathrm{sq}$ range, with CTO films exhibiting cross-grain mobilities of $>60{\mathrm{cm}}^2/\mathrm{V}\text{-}\mathrm{s}$ and a carrier density of ${\sim 10}^{19}/{\mathrm{cm}}^3$ . An HRT film is deposited on the TCO as a buffer layer to reduce leakage current and improve CdS film quality. Undoped tin oxide and ZTO (or Zn-doped tin oxide) have been successfully used as HRT layers at thicknesses in the 30-nm range. Since CdS typically does not contribute photocurrent to the cell, its 2.4-eV bandgap causes parasitic absorption at wavelengths $<500\mathrm{nm}$ , and for this reason, its thickness needs to be reduced as much as possible. CdS can be deposited by numerous methods, including VTD, CSS, sputtering, and chemical bath deposition. Incorporating oxygen into the CdS film ¹⁶ during growth improves CdS film durability ²³ to high CdTe deposition temperature by reducing vapor pressure and diffusivity, allowing ultrathin CdS films to be employed, with final thickness being $<30\mathrm{nm}$ .

2.3.

Cl-Treatment

As-deposited CdTe films contain extended and point defects and are of poor electronic quality. For example, VTD CdTe films formed at 580 to 600°C at a rate of $10\mu \text{m}/\min$ exhibit grains with $1:1$ aspect ratio, and weak p-type conduction with low mobility and low carrier concentration of $<{10}^{14}/{\mathrm{cm}}^3$ . Time-resolved photoluminescence (TRPL) analysis of such films at the CdS interface showed a minority carrier effective lifetime of $<1\mathrm{ns}$ . ²⁴ In another study on CSS grown CdTe layers, a high grain boundary recombination velocity of $\sim {10}^4\mathrm{cm}/\mathrm{s}$ was recently estimated from the cathodoluminescence data. ²⁵

Following the CdTe deposition step, the entire film stack is subjected to a thermal treatment at a temperature around 400°C in the presence of ${\mathrm{CdCl}}_2$ and oxygen. This treatment drastically reduces CdTe extended defect density, increases p-type conductivity (acceptor density reaching ${10}^{14}/{\mathrm{cm}}^3$ level), and passivates the grain surfaces, increasing the effective minority carrier lifetimes to $>3\mathrm{ns}$ . It should be noted that a TRPL second decay constant (which is related to lifetime) ²⁶ of 10 to 15 ns was recently reported for the 18 to 19% efficient devices. ²⁷ High temperature deposition, Cl-treatment, and grain boundary diffusion promote interdiffusion at the CdS/CdTe interface and convert this interface into a ${\mathrm{CdS}}_{1-y}{\mathrm{Te}}_y/{\mathrm{CdTe}}_{1-x}{\mathrm{S}}_x$ junction, where the values of $x$ and $y$ depend on the temperature reached and are typically $x\sim 0.05$ and $y\sim 0.03$ . Alloying reduces the lattice mismatch at the junction from $\sim 11$ to $\sim 9\%$ and decreases the energy gap slightly on each side of the junction due to the optical bowing parameter induced by nonideal mixing. ¹³

2.4.

Doping and Contacting

Cl-treatment leaves a mixture of native oxides (CdO, ${\mathrm{CdTeO}}_3$ , ${\mathrm{CdTe}}_2{\mathrm{O}}_5$ ) and Cd- and Te- oxychlorides on the CdTe surface. After removing these residues, a Cu source layer is typically deposited on the clean surface and the dopant is driven into the CdTe layer through moderate annealing. Copper source layers include Cu-doped graphite paste and low-resistivity compounds, such as ${\mathrm{Cu}}_2\mathrm{Te}$ and Cu-doped ZnTe, that form low-resistance primary contacts with contact potential barriers $<0.3\mathrm{eV}$ . Amount of Cu introduced is critical and has an optimum value based on the device structure ²⁸ and the nature of the CdTe layer. After the doping step, high-efficiency devices are reported ²⁷ to have an ionized acceptor density in the range of 0.5 to $1\times {10}^{15}/{\mathrm{cm}}^3$ . A large volume of literature exists on the role of Cu in CdTe solar cells, including its interaction with defects, its distribution in the cell structure, and its influence on minority carrier lifetime and cell stability. The reader is referred to Refs. 29 and 30 for a recent discussion of some of these topics. After the doping step, a robust secondary contact is deposited over the primary contact layer to facilitate lateral current collection. The secondary contact may be a single metal film, such as Au, Ni, or Mo, in the laboratory devices; however, for longer-lifetime contacts, a diffusion buffer layer may first be deposited. Nitrides of refractory metals, such as MoN and TiN, act as good barriers. Once the barrier is deposited, lower-cost metals, such as Al, can be used for lateral conduction. ${\mathrm{MoO}}_{\mathrm{x}}$ has recently been investigated as a high work function buffer layer in CdTe cell contacts. ³¹

2.5.

Recent Superstrate Cell Results

Recent progress in CdTe cell efficiency has been rapid. ²⁷ In 2011, First Solar announced a 17.3% efficient cell. Then, in 2012, GE Global Research Center (GE) revealed a verified 18.3% efficient device, which was followed by an 18.7% cell by First Solar. In early 2013, GE announced a 19.6% device. In mid-2013, First Solar acquired the GE technology and, in 2014, announced a new champion cell with 20.4% efficiency. ⁵ Current–voltage characteristics of the 18.7% device and the quantum efficiency (QE) data for the 17.3, 18.3, and 18.7% devices can be found in Ref. 27 [also see Fig. 2(a) below]. Parameters of the 19.6% device ³² were ${\mathrm{V}}_{\mathrm{oc}}=857.3\mathrm{mV}$ , $J_{\mathrm{sc}}=28.59\mathrm{mA}/{\mathrm{cm}}^2$ , $\mathrm{FF}=0.80$ . Unfortunately, there are no details about these highly efficient devices. However, improvements in efficiency seem to be marked by gains in $J_{\mathrm{sc}}$ , most probably by modification of the glass type/thickness, an optimized AR coating as well as modifications to the window layer stack to achieve more optical throughput. It should be noted that the $J_{\mathrm{sc}}$ value of the 16.7% device from National Renewable Energy Laboratory (NREL) was $26.1\mathrm{mA}/{\mathrm{cm}}^2$ , whereas this value is improved to $28.59\mathrm{mA}/{\mathrm{cm}}^2$ for the recent 19.6% efficient cell. The voltage improvement was only $\sim 12\mathrm{mV}$ .

Fig. 2

(a) Quantum efficiency (QE) versus wavelength comparison of five different cells. (b)  ${\log }_{10}$ QE versus energy data for the cells of (a).

The QE of Institute of Energy Conversion (IEC) 2013 (16%), NREL 2001 (16.7%), First Solar 2011 (17.3%), and GE 2012 (18.3%) devices are compared in Fig. 2(a), where the QE is plotted over the entire range of wavelengths, and in Fig. 2(b), where ${\log }_{10}\mathrm{QE}$ versus energy relationship near the absorber band gap is shown. The IEC cell employed a Corning engineered low-sodium glass, a ZTO/CTO stack, and a 60-nm-thick CdS layer. The impressive $J_{\mathrm{sc}}$ improvement in the GE device is due to the refinement of the window stack, increasing the UV and blue response, resulting in a square QE from the glass cutoff to the CdTe band gap. It is clear that the higher current densities of the other cells in Fig. 2(a) are also due to more transparent window, First Solar cells reaching deeper into the UV region. At 1.5-eV cutoff, the maximum AM1.5 photocurrent for CdTe is $\sim 30.5\mathrm{mA}/{\mathrm{cm}}^2$ . To get closer to the practical current density goal of $30\mathrm{mA}/{\mathrm{cm}}^2$ , one can use even thinner and more transparent glass superstrate and/or narrow the CdTe band gap so that the long wavelength response extends $\sim 15\mathrm{nm}$ more, potentially adding another $1\mathrm{mA}/{\mathrm{cm}}^2$ to the current. One way of reducing the bandgap of CdTe is to alloy it with CdS and/or CdSe. Although both of these materials have higher bandgap values than CdTe, the ${\mathrm{CdTe}}_{1-x}{\mathrm{S}}_x$ and ${\mathrm{CdTe}}_{1-x}{\mathrm{Se}}_x$ alloys display bandgap values smaller than CdTe for $x$ values $\ll 0.1$ . For the case of S, an $x$ value of $\sim 0.03$ would be adequate for 15-nm extension of the QE. For the case of CdSe, an $x$ value of $\sim 0.05$ would be adequate. It should be noted that ${\mathrm{CdTe}}_{1-x}{\mathrm{Se}}_x$ crystals have enhanced charge transport properties compared to CdTe crystals, ³³ and the lattice constant of CdSe ( $6.05Å$ ) is between CdS ( $5.83Å$ ) and CdTe ( $6.48Å$ ). Use of a Cd-Se-S or CdSe/CdS junction-partner would allow alloying of the CdTe absorber with both S and Se during the ${\mathrm{CdCl}}_2$ treatment step and reduce the lattice mismatch further.

4.1.

Recent Module Results

After the demonstration of the first 11% CdTe module in 2000, ¹¹ the biggest jump in efficiency came in early 2012 when First Solar reported a 14.4% efficient device. In early 2013, the efficiency was improved to 16.1%, and a 17% (17.5% aperture area) module was announced ³⁵ in March 2014. QE data of the 16.1% module ³² show appreciable current loss in the UV-blue region of the spectra compared to the high-efficiency cells reported around the same time. Clearly, the stack used in the module was different from the one in the cells. No data are yet available about the 17% module to see where the improvement came from. The details of the champion module process flow are important to be able to assess how the large gap between the champion cell efficiencies ( $\sim 20\%$ ) and the efficiencies of the commercial modules (13 to 14%) can be reduced without increasing cost of manufacturing appreciably.

4.2.

Monolithic Integration

There are two monolithic integration methods that have been employed in CdTe module fabrication. In the first approach ³⁶ shown in Fig. 3, the process flow includes deposition of a TCO layer, formation of the P1 scribe lines, deposition of the CdS/CdTe stack, formation of the P2 scribe lines, deposition of a back-contact, and formation of the P3 scribe lines.

Fig. 3

Module structure with a CdTe bridge between transparent-conductive-oxide (TCO) pads.

Diode pumped solid-state lasers with nanosecond pulses are commonly used for the scribing steps, ³⁷ and the laser beam preferably enters from the glass side. For $\sim 50\text{-}\mu \text{m-}\text{wide}$ scribes and 50 μm distance between them, the total width of the dead zone in Fig. 3 can be in the order of 250 to 350 μm, taking into account the heat-affected areas and the inaccuracies in positioning and parallelism. For a 10-mm-wide cell, this corresponds to a current loss of $\sim 3\%$ . Obviously, there have been ongoing efforts to reduce the scribe widths to $<25\mu \text{m}$ and to decrease the size of the dead zone. ³⁸ The possibility of shunting through the CdTe bridge is a shortcoming of this method. Shunting may result from defects in the bridge area due to poor nucleation and growth of the CdS and/or the CdTe layer(s) onto the exposed glass surface and due to impurity diffusion from glass and impurity accumulation during the processes described in Secs. 2.3 and 2.4. For a technology like ED, it is not even possible to grow a uniform CdTe layer at or around the P1 scribe lines because of lack of a highly conductive surface underneath.

In an alternative integration approach ³⁹ that was employed in early modules, ⁴⁰ a TCO/CdS/CdTe stack is first deposited and then the P1 scribe lines are formed through the whole stack. Then a resist is dispensed into the P1 lines. The process continues with the formation of the P2 scribe lines, contact deposition, and the formation of the P3 scribe lines. The challenge with this integration technique is dispensing a resist into a large number of P1 scribe lines in a fast, repeatable, and economical manner without leaving any uncovered area that would later cause a shunt, while trying to minimize the area of the dead zone. This important problem was overcome by the development of a photoresist plug integration process, which has been very successful.

The photoresist plug integration process was developed by Basol ⁴¹ and applied to cells and small submodule circuits fabricated by the ED technique ¹⁰ at Monosolar. The idea was to indiscriminately fill any opening in the electroplated CdS/CdTe stack with an insulating resist rapidly and with $\sim 100\%$ yield. The process was later transferred to BP Solar and used for the fabrication of the 11% module, ¹¹ although the details of this process was not published. As shown in Fig. 4(a), the first step in the photoresist plug technique is deposition of a TCO/CdS/CdTe stack followed by the formation of the P1 scribe lines. Then a negative photoresist material is coated over the surface, filling the P1 scribe lines as shown in Fig. 4(b). The next step is light exposure through the glass, which results in the exposure and cross-linking of the resist within the P1 scribe lines. The CdTe film, acting as an opaque mask, protects the resist layer at the top surface from getting exposed. Treating the structure by a resist developer removes the unexposed resist from the CdTe surface and leaves the hardened photoresist plugs in the P1 scribe lines only. The process may then proceed through the formation of the P2 scribe lines and the deposition of the back-contact [Fig. 4(c)]. Final device structure is obtained after the formation of the P3 scribe lines [Fig. 4(d)]. The monolithically integrated module structure of Fig. 4(d) has many advantages and, to the best of the authors’ knowledge, is the approach that has been widely adapted, with vendors offering in-line systems to carry out the photoresist deposition (by spraying or rolling), exposure, development, and rinse steps. The resist plugs in Fig. 4(d) do not allow any shunts between the TCO pads irrespective of the CdTe resistivity or the scribe line width. Furthermore, the height and shape of the plugs can be manipulated by adjusting the viscosity/thickness of the photoresist and the exposure time/intensity. For example, mushroom-shaped plugs, which can insulate the damaged region around the P1 scribe lines, can be formed by using thicker resist layers and longer exposure times. Through such optimization, the photoresist plug integration process minimizes the dead zone while providing good electrical isolation. It also passivates any pinholes that may be present within the cells.

Fig. 4

Photoresist plug integration process flow for monolithic integration: (a) deposit TCO/CdS/CdTe stack and form P1 scribe lines, (b) cover the surface with photoresist and expose through the glass superstrate, (c) develop and rinse forming the photoresist plugs, form P2 scribe lines, deposit back contact, (d) form P3 scribe lines.

4.3.

Field Performance of Modules

CdTe is a relatively new PV product. Although indoor and outdoor stability tests of early modules and small systems have been carried out for many years, ^{42 , 43} deployment of commercial modules in relatively large fields has only about a 10-year history. While efforts are underway to increase the CdTe performance as measured under standard test conditions, it is also essential to model the behavior of these devices under real deployment conditions in various geographical locations. A recent indoor study of the effect of temperature on power output of modules showed a temperature coefficient of $-0.21\%/°\mathrm{C}$ for CdTe compared to $-0.45\%/°\mathrm{C}$ for Si. ⁴⁴ Another report on modules deployed outside in Spain showed an average temperature coefficient of $-0.35\%/°\mathrm{C}$ , which varied widely between summer and winter months ⁴⁵ due to the effect of solar spectrum variation on the energy yield of CdTe. ⁴⁶ In another outdoor study, ⁴⁷ the annual average daily yield of CdTe modules ( $\sim 5.4\mathrm{Wh}/\mathrm{Wp}$ ) was found to be somewhat higher than poly-Si modules ( $\sim 5.3\mathrm{Wh}/\mathrm{Wp}$ ) and the daily efficiency decreases were smaller for CdTe ( $\sim 5.4\%$ ) compared to poly-Si (7.6%) since modules operated mostly under high irradiation conditions. Janke and Strasser, ⁴⁸ however, could not confirm higher yields for CdTe modules in their measurements. Comparison of the DC performance loss rates for 12 different grid connected systems operated in Cyprus showed that the average annual performance loss rate for the CdTe modules of vintage 2006 was $\sim 2.3\%$ . ⁴⁹ It is clear that much more data is necessary to improve the models for predicting the energy yield of a CdTe system, especially since the technology itself has been continually changing and some of the results quoted above were obtained using old vintage modules. Other phenomena, such as transient effects in modules, ^{50 , 51} also need to be further studied.