Correlator receiver architecture with PnpN optical thyristor operating as optical hard-limiter

Tae-Gu Kang; Su Ho Lee; Soonchul Park

doi:10.1117/1.3599875

1 July 2011 Correlator receiver architecture with PnpN optical thyristor operating as optical hard-limiter

Tae-Gu Kang, Su Ho Lee, Soonchul Park

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Optical Engineering, Vol. 50, Issue 7, 075004 (July 2011). https://doi.org/10.1117/1.3599875

Abstract

We propose novel correlator receiver architecture with a PnpN optical thyristor operating as optical hard-limiter, and demonstrate a multiple-access interference rejection of the proposed correlator receiver. The proposed correlator receiver is composed of the 1×2 splitter, optical delay line, 2×1 combiner, and fabricated PnpN optical thyristor. The proposed correlator receiver enhances the system performance because it excludes some combinations of multiple-access interference patterns from causing errors as in optical code-division multiple access systems with conventional optical receiver shown in all previous works. It is found that the proposed correlator receiver can fully reject the interference signals generated by decoding processing and multiple access for two simultaneous users.

©(2011) Society of Photo-Optical Instrumentation Engineers (SPIE)

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Tae-Gu Kang, Su Ho Lee, and Soonchul Park "Correlator receiver architecture with PnpN optical thyristor operating as optical hard-limiter," Optical Engineering 50(7), 075004 (1 July 2011). https://doi.org/10.1117/1.3599875

Published: 1 July 2011

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KEYWORDS

Receivers

Optical correlators

Signal processing

Signal detection

Channel projecting optics

Binary data

Optical engineering

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