This paper examines the impact of submicron metal oxide semiconductor (MOS) integrated circuit technology on submicron lithography, and contrasts the lithography picture today with that for submicron features. A considerably larger number of factors must be dealt with rigorously because they either do not scale with decreasing dimensions or they do not lend themselves easily to more rigid control so that it has become disproportionately difficult to reduce their effect. In addition to the lithography issues, other serious device technology limitations arise at submicron dimensions. These have to do with device isolation, gate insulation, parasitic resistance and capacitance, interconnectivity, particle-induced upset, and hot electron effects. These issues must also be successfully resolved if submicron dimensions are to be successfully exploited in submicron integrated circuits.
Al F. Tasch, Jr.,
"Metal Oxide Semiconductor Technology Scaling Issues And Their Relation To Submicron Lithography," Optical Engineering 22(2), 222176 (1 April 1983). https://doi.org/10.1117/12.7973077