1 October 1986 Optical Clock Distribution To Silicon Chips
Author Affiliations +
Optical Engineering, 25(10), 251103 (1986). doi:10.1117/12.7973964
Timing constraints for state-of-the-art very large scale integrated circuits (VLSI) in silicon are rapidly approaching communication limits available with layered two-dimensional metal and polysilicon wiring approaches. For such communication-limited systems, reliable clock distribution is a key concern. The range of finite differences in signal delays over clock wires of various lengths for large chips creates a timing skew that is significant when compared to the switching time of transistors in the circuit. The high bandwidth and three-dimensionality of imaging optical systems suggest that optical clock distribution systems have the potential to overcome the timing barriers presented by planar wiring. Clock signals can be holographically mapped to detector sites within small functional cells on a chip surface. Within each functional cell, the clock is distributed with negligible delays via surface wires, reducing skew effects to the variation in reaction times of the photodetectors on the chip. This paper includes the presentation of an optical clock distribution system assuming holographic mapping of beams from an off-chip optical source. Computer simulations of the electronic response of optical clock detection circuits in standard 4 µm CMOS technology have been performed.
Bradley D. Clymer, Joseph W. Goodman, "Optical Clock Distribution To Silicon Chips," Optical Engineering 25(10), 251103 (1 October 1986). https://doi.org/10.1117/12.7973964


Fabrication of Organic complementary inverter
Proceedings of SPIE (October 15 2012)
Fault-Tolerant VLSI Systolic Arrays and Two-Level Pipelining
Proceedings of SPIE (November 28 1983)
Temperature effects on circuit synchronism
Proceedings of SPIE (June 30 2005)
Optical Clock Distribution To Silicon Chips
Proceedings of SPIE (June 09 1986)

Back to Top