The paper describes the design and development of a CCD shift register that can take analog samples of an electrical signal at rates up to 1 x 108 samples/s and provide temporary storage for 1024 samples. It is intended for operation in a fast-in, slow-out mode for capturing high speed electrical transients. The requirements of fast clocking and moderate clock driver power led to the choice of a serial-parallel-serial design. The CCD chip contains four storage arrays that form two differential channels. Differential operation provides good linearity. The two channels can be used independently or multiplexed for sampling at the highest rate. The CCD is of the buried-channel type and uses four-phase clocking on all registers. It is fabricated using a modified NMOS process, with two polysilicon layers to provide an overlapping transfer gate structure. Operating characteristics of the CCD are described, together with its behavior in an instrument environment. For optimum performance the CCD chip is mounted on a hybrid, together with clock driver ICs. Such devices are used in the signal acquisition section of a digital storage instrument that was developed recently.