Fully parallel processors call for a technology that is inherently parallel, a suitable number system, and an efficient encoding scheme for handling the data. The throughput of a binary adder/subtractor is limited by the carry propagation to the most significant bits. Optical adders using a modified signed digit (MSD) number system have been proposed to eliminate the carry propagation chain encountered in binary adders. The MSD number system satisfies the requirements of fully parallel addition/subtraction by limiting the carry propagation to two positions to the left. This enables one to carry out the addition/subtraction of two n-digit MSD numbers in three stages, independent of n. In this paper it is shown that by suitably exploiting the redundant nature of the MSD number system, the carry generation and propagation can be completely eliminated. The MSD adder/subtractor presented in this paper fully exploits the redundant nature of the MSD number system and performs the addition/subtraction of two numbers in a single stage. The adder employs 81 substitution rules to perform the addition/subtraction of two MSD numbers in a single stage. The number of substitution rules can be reduced to 16 if the input numbers are limited to binary. The proposed architecture reduces the computation time by 33.3% compared to the three-stage MSD adder originally proposed.