The power dissipation for large-area high-speed charge-coupled device (CCD) arrays is analyzed. The four mechanisms responsible for power dissipation in a CCD are carrier lift and friction within the CCD channel, load currents through the on-chip output amplifiers, capacitive charge and discharge currents through the epitaxial layer or substrate, and currents flowing through the polysilicon clock register electrodes. These processes are easily calculated for small or slow devices. For large high-speed devices, on the other hand, the conventional analytical techniques are inadequate. The large device area leads to high resistive-capacitive constants in the parallel clock registers, causing clock pulses to degrade in shape as they travel along a clock electrode. A distributed system analysis based on lumped circuit parameters for each pixel is necessary to calculate the current and thus the power dissipated at each point on the surface of the COD. A computer simulation of a standard frame-transfer CCD was performed using SPICE software. The results of the simulation indicate a much lower power dissipation than previously assumed and also point out various problems with conventional device architectures for large-area high-speed CCDs.