1 June 1996 Demonstration of an optoelectronic interconnect architecture for a parallel modified signed-digit adder and subtracter
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Optical Engineering, 35(6), (1996). doi:10.1117/1.600752
Abstract
A space-position-logic-encoding scheme is proposed and demonstrated. This encoding scheme not only makes the best use of the convenience of binary logic operation, but is also suitable for the trinary property of modified signed-digit (MSD) numbers. Based on the spaceposition- logic-encoding scheme, a fully parallel modified signed-digit adder and subtracter is built using optoelectronic switch technologies in conjunction with fiber-multistage 3-D optoelectronic interconnects. Thus an effective combination of a parallel algorithm and a parallel architecture is implemented. In addition, the performance of the optoelectronic switches used in this system is experimentally studied and verified. Both the 3-bit experimental model and the experimental results of a parallel addition and a parallel subtraction are provided and discussed. Finally, the speed ratio between the MSD adder and binary adders is discussed and the advantage of the MSD in operating speed is demonstrated.
DeGui Sun, Na-Xin Wang, Li-Ming He, Zhao-Heng Weng, Daheng Wang, Ray T. Chen, "Demonstration of an optoelectronic interconnect architecture for a parallel modified signed-digit adder and subtracter," Optical Engineering 35(6), (1 June 1996). https://doi.org/10.1117/1.600752
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