1 March 1997 Extension and very large scale integration implementation of the majority-gate algorithm for gray-scale morphological operations
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Optical Engineering, 36(3), (1997). doi:10.1117/1.601140
Abstract
This paper presents the design and VLSI implementation of a new ASIC that performs in real time the morphological operations of dilation and erosion. The ASIC’s architecture is based on the extension of the majority-gate algorithm for morphological operations. The ASIC was implemented using a DLM, 0.7-?m, CMOS, N-well process, and it occupies a silicon area of 14.78 mm2. Its maximum speed of operation is 92.5 MHz. Targeted applications include machine vision, where the need for short processing times is crucial.
Antonios C. Gasteratos, Ioannis Andreadis, Phillippos G. Tsalides, "Extension and very large scale integration implementation of the majority-gate algorithm for gray-scale morphological operations," Optical Engineering 36(3), (1 March 1997). http://dx.doi.org/10.1117/1.601140
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KEYWORDS
Image processing

Very large scale integration

Image resolution

Mathematical morphology

Binary data

Signal processing

Multiplexers

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